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In todays world DFT (Design For Test) is an no-excuse and design teams struggle hard to cover all the portions of the design to eliminate the defects
caused due to manufacturing . The science behind this is Designing for Test, rather it goes with the article , how to design rtl which is friendly to DFT. What all we can think up-front to make sure that the turn-around time to perform scan-insertion is less and we dont see the warnings in our test-insertion
tool and then go back to RTL to ensure that we have coded our logic and our constructs are friendly enough for execution. Some of the DFT violations include
Modelling Violations
Improperly driven three-state violations
Asynchronous signal active during scan violations
Flop clock/set/reset input not controlled
Latch clock/set/reset input not controlled
RAM write input not controlled
clock cannot capture data
clock input not active when it is active
clock goes to data input
clock goes to both data and clock inputs
clock get connected to multiple clock/set/reset inputs
clock input could not capture data
bus gate failed contention check
bus gate failed state check
Latch not-transparent
clock connected to primary output violation
Unstable cell clock input connected from multiple sources violation
bi-directional bus driver enable affected by scan cell violation Some of the methodologies to be followed, during RTL stage, to have a DFT friendly RTL. The below image shows, how to make the enable of the clock-gate always active so that clock will not be blocked in the flip flop clock pin.We need to make the test-enable to one during test-mode. 
The image shows, how to pass the scan clock during scan-mode. 
The image shows, how not to block the preset or clear during scan-mode. 
The below image shows , how to bypass the clock during test-mode, incase of synchronizing clocks. 
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how to write dft friendly rtl
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